1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a static random access memory device, which is resistant to a software error that would otherwise be caused by exposure to .alpha. rays, for example, and a method of manufacturing such a semiconductor memory device.
2. Description of the Prior Art
As shown in FIG. 1 of the accompanying drawings, one conventional semiconductor memory device, such as a static random access memory (SRAM) device, has a memory cell composed of a flip-flop FF comprising a pair of driver transistors Tr.sub.1, Tr.sub.2 such as N-channel MOS transistors and a pair of high-resistance loads R.sub.1, R.sub.2 connected respectively to storage nodes N.sub.1, N.sub.2 of the driver transistors Tr.sub.1, Tr.sub.2, and a pair of access transistors Q.sub.1, Q.sub.2 such as N-channel MOS transistors. To the memory cell, there are connected a word line WL and bit lines BL.
The physical structure of the conventional SRAM shown in FIG. 1 is shown in FIG. 2 of the accompanying drawings. The driver transistor Tr.sub.1 has a gate electrode G.sub.1, and the access transistor Q.sub.2 has a gate electrode 21 which serves as part of the word line WL. These gate electrodes G.sub.1, 21 are formed by a first layer of polycrystalline silicon. A layer 23 of polycrystalline silicon which serves as the high-resistance load R.sub.2 is disposed over the gate electrode G.sub.1 with an interlayer insulating film 22 interposed therebetween.
The polycrystalline silicon layer 23 and the gate electrode G.sub.1 are connected to each other on a drain region 24 of the access transistor Q.sub.2, the junction between the polycrystalline silicon layer 23 and the gate electrode G.sub.1 serving as the storage node N.sub.1 shown in FIG. 1. The access transistor Q.sub.2 has a source region 25 to which the bit lines BL are connected. Aluminum interconnections 26 are disposed over the polycrystalline silicon layer 23 and a capacitor plate electrode 27, and connected to the polycrystalline silicon layer 23 and the capacitor plate electrode 27 at certain intervals.
To prevent the SRAM from suffering a software error due to exposure to .alpha. rays, for example, capacitors C.sub.1, C.sub.2 are connected between the storage nodes N.sub.1, N.sub.2 and ground as shown in FIG. 1. In FIG. 2, the capacitors C.sub.1, C.sub.2 are provided by the capacitor plate electrode 27 which is positioned over the junction between the polycrystalline silicon layer 23 and the gate electrode G.sub.1 with a dielectric film interposed between. The capacitor plate electrode 27 is connected to a ground line (not shown) by an interconnection layer.
Since it is necessary to ground the capacitors C.sub.1, C.sub.2, the capacitor plate electrode 27 is required to be connected to the ground line by the interconnection layer.
The conventional SRAM therefore needs an extra region for the interconnection layer to connect the capacitor plate electrode 27 to the ground line. The fabrication process for the SRAM requires a step of defining an opening through which the interconnection layer can contact capacitor plate electrode 27 and the ground line. Therefore, the fabrication process is relatively complex, and the SRAM is relatively expensive to fabricate.